#18 Timing control in verilog | Delay based, Event based,Level sensitive timing control with example

In this verilog tutorial various timing control such as delay based timing control, event based timing control and level sensitive timing control has been explained in details with verilog code.it has also covered inter assignment, intra assignment , zero delay control and named event control delay. Lesson-1 Why verilog is a popular HDL https://youtu.be/p24rw09SeG4 Lesson-2 Operators in verilog(part-1) https://youtu.be/MghcEyERtL8 Lesson-2 Operators in verilog(part-2) https://youtu.be/ELILGxgwr1g Lesson-2 Operators in verilog(part-3) https://youtu.be/lQ-Kgyz0a0E Lesson-3 Syntax in verilog https://youtu.be/ykP6WYPaInU Lesson-4 Data types in verilog https://youtu.be/6kugODBZ40s Lesson-5 Vector and Array in verilog https://youtu.be/9GGN2SeqzVU Lesson-6 Modules and port in verilog https://youtu.be/XAWQ_2rtC3I Lesson-7 Gate level modelling in verilog https://youtu.be/gX3rDD1I3ms Lesson-8 Dataflow Modeling in verilog https://youtu.be/Bmxl0bk-W_c Lesson-9 Behavioral Modeling in verilog https://youtu.be/KgSO06yKIJo Lesson-10 Structural Modeling in verilog https://youtu.be/Zk2mCKowUt4 Lesson-11 always block in verilog https://youtu.be/-PCHSFyszoc Lesson-12 always block for combinational logic https://youtu.be/MRnWHIw22Eo Lesson-13 sequential logic in design https://youtu.be/k7q-SZm03ok Lesson-14 always block for sequential logic https://youtu.be/28QURvvWl84 Lesson-15 Difference between latch and flip flop https://youtu.be/jcfQIapfxcw Lesson-16 Synchronous and Asynchronous RESET https://youtu.be/uB4s1X6nsz8 Lesson-17 Delays in verilog https://youtu.be/7evM0YFb5Z8 Lesson-18 Timing control in verilog https://youtu.be/9FVyHBglOEI Lesson-19 Blocking and Nonblocking assignment https://youtu.be/CcbnWqL2Vi8 Lesson-20 inter and intra assignment delay in verilog https://youtu.be/CLoSp8ElEZ8 Lesson-21 Why delays are not synthesizable https://youtu.be/0abLed5QFV8 Lesson-22 TESTBENCH writing in verilog https://youtu.be/Urvo2C_mniI Lesson-23 Multiple always block in verilog https://youtu.be/X5vfOzSHcHI Lesson-24 INITIAL block in verilog https://youtu.be/Mzb4LQcWzqg Lesson-25 Difference between INITIAL and ALWAYS block in verilog https://youtu.be/4tPTu-RZbgI Lesson-26 if else in verilog https://youtu.be/LnfFM_qbNJw Lesson-27 CASE statement in verilog https://youtu.be/S9M2TgpVzI4 Lesson-28 CASEX and CASEZ in verilog https://youtu.be/1WeP_wygvVU Lesson-29 FOR loop in verilog https://youtu.be/8kLXfgS5MaQ Lesson-30 WHILE loop in verilog https://youtu.be/tsWVKW0tnME Lesson-31 FOREVER in verilog https://youtu.be/DKH-ZDmu3LM Lesson-32 REPEAT in verilog https://youtu.be/tfoWqBKlbQM Lesson-33 GENERATE in verilog https://youtu.be/_ZsWz-JjRbU Lesson-34 FORK-JOIN in verilog https://youtu.be/swXtn8aSJhU Lesson-35 named block in verilog https://youtu.be/Sd2J9KCcIW0 Lesson-36 TASK in verilog https://youtu.be/XZzJRDXBf5k Lesson-37 FUNCTION in verilog https://youtu.be/pK1avYPg3NY Lesson-38 WIRE vs REG in verilog https://youtu.be/NfFa_uwDVhs Lesson-39 FSM-MEALY state machine in verilog https://youtu.be/DgvTYv2OvBQ Lesson-40 FSM- MOORE state machine in verilog https://youtu.be/bE-FUcyctlQ My mail id - [email protected] Please, don't send me mail asking for content(PPT,PDF) or any verilog code. For any other help you are most welcome. ***** Happy Learning ***** Don't forget to LIKE, subscribe 🔔 and comments.