4-Layer PCB Stackup Strategy — SGPS, Return Currents, EMI & Controlled Impedance Explained

The four-layer stackup isn't just "more layers." The arrangement of those layers — which one carries ground, how close it sits to the signal layer, and whether any splits break the reference — determines whether your high-speed signals behave or fail EMC testing. This lecture covers the physical construction of a four-layer board, the SGPS layer arrangement and why it's the standard, the return current physics that make a solid ground plane on L2 so consequential, the quantified advantages over a two-layer board, common alternatives to SGPS and when to use them, and five rules that govern how a four-layer stackup translates into a working board. 🎓 Course: KiCad Advanced — BGA, Signal Integrity, and High-Speed Layout Full enrollment and course details: https://connect.techexplorations.com/so/smart-usb-thumb-drive-with-kicad This course takes you through the complete design of a Smart USB Thumb Drive — from schematic to manufactured PCB — using KiCad. You'll work with BGA packaging, USB differential pairs, eMMC length matching, and ideal diode power management on a real, orderable board. In this video The four-layer stackup in theory and practice — physical construction, the SGPS arrangement, return current behaviour, quantified EMI and impedance advantages, stackup alternatives, and the five rules to carry into every four-layer design decision. Timestamps 00:00 Introduction — why the project board moved from two layers to four 00:31 What this lecture covers and why understanding four-layer strategy sharpens two-layer thinking 03:05 Physical construction — core, prepreg, inner and outer layers, single lamination press cycle 04:59 Standard board specs — 1.6 mm total thickness, copper weights, symmetry requirement 05:45 The SGPS arrangement — signal, ground, power, signal, and why it's the standard 06:09 Why ground on L2 is the most consequential decision — thin dielectric, tight reference coupling 07:56 Return current behaviour above 10 MHz — path of least inductance, loop area, and loop inductance 09:27 Quantified comparison — 1–2 nH loop inductance on a four-layer board vs 10–20 nH on two layers 10:23 What a split in the ground plane does — return current detour, enlarged loop area, EMC failures 11:04 Five compounding advantages of SGPS — 15 dB EMI reduction, controlled impedance, reduced crosstalk, power distribution, routing density 13:43 Common misconception — inter-plane capacitance at standard core thickness does not replace discrete decoupling capacitors 14:23 Alternatives to SGPS — double ground for maximum signal integrity, shielded signal for sensitive analog, split power planes for multiple voltage rails 16:09 Power on L2 — when it's acceptable and when the standard SGPS arrangement is preferred 17:34 When to move beyond four layers — what a six-layer board adds 18:11 Five rules for four-layer stackup design — ground reference, plane splits, stitching vias, fabricator data, symmetry 21:22 Summary Tech Explorations creates practical electronics and PCB design courses for engineers, makers, and educators. More courses at techexplorations.com.