4.3(c) - Combinational Logic Synthesis: SOP Design Example

You learn best from this video if you have my textbook in front of you and are following along. Get the book here: https://amzn.to/32IbAaN. This video covers a portion (see title of video!) of the textbook "Introduction to Logic Circuits & Logic Design with VHDL" by Brock LaMeres. I also have a Verilog version of this textbook, which you can get here: https://amzn.to/2FDCs2Q.