8086 Pin Configuration in Microprocessor || Ekeeda.com

"8086 Pin Confinguration Power supply and frequency signals:- It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for its operation. Clock signal:- Clock signal is provided through Pin-19. It provides timing to the processor for operations. Address/data bus :-AD0-AD15. These are 16 address/data bus. AD0-AD7 carries low order byte data and AD8AD15 carries higher order byte data. Address/status bus :- A16-A19/S3-S6. These are the 4 address/status buses. During the first clock cycle, it carries 4-bit address and later it carries status signals. S7/BHE :-BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of data using data bus D8-D15. Read($\overline{RD}$) :- It is available at pin 32 and is used to read signal for Read operation. Ready :- It is available at pin 32. It is an acknowledgement signal from I/O devices that data is transferred. RESET :- It is available at pin 21 and is used to restart the execution. INTR :- It is available at pin 18. It is an interrupt request signal, which is sampled during the last clock cycle of each instruction to determine if the processor considered this as an interrupt or not. NMI :- It stands for non-maskable interrupt and is available at pin 17. MN/$\overline{MX}$ :- It stands for Minimum/Maximum and is available at pin 33. INTA :- It is an interrupt acknowledgement signal and id available at pin 24. ALE :- It stands for address enable latch and is available at pin 25. DEN :- It stands for Data Enable and is available at pin 26. DT/R :- It stands for Data Transmit/Receive signal and is available at pin 27. M/IO :- This signal is used to distinguish between memory and I/O operations. WR :- It stands for write signal and is available at pin 29. HLDA :- It stands for Hold Acknowledgement signal and is available at pin 30. HOLD :- This signal indicates to the processor that external devices are requesting to access the address/data buses. It is available at pin 31 QS1 and QS0 :- These are queue status signals and are available at pin 24 and 25. S0, S1, S2:- These are the status signals that provide the status of operation, which is used by the Bus Controller 8288 to generate memory & I/O control signals. LOCK :- When this signal is active, it indicates to the other processors not to ask the CPU to leave the system bus. RQ/GT1 and RQ/GT0 :- These are the Request/Grant signals used by the other processors requesting the CPU to release the system bus. #OnlineLectures #EducationForFree #FullHD #HappyLearning #Engineering Thanks For Supporting Us Website - http://ekeeda.com Parent Channel - https://www.youtube.com/c/ekeeda Facebook - https://www.facebook.com/ekeeda.video Twitter - https://twitter.com/Ekeeda_Official Blogger - http://ekeeda.blogspot.in Pinterest - https://in.pinterest.com/ekeedavideo Digg - http://digg.com/u/ekeeda_Video Tumbler - https://www.tumblr.com/blog/ekeedavideo Reddit - https://www.reddit.com/user/ekeeda_Video LinkedIn- https://www.linkedin.com/in/ekeeda-video-4a5b83124 Happy Learning : ) -~-~~-~~~-~~-~- Please watch: "19 Problem 6 on SFD and BMD for the beam as shown in figure" https://www.youtube.com/watch?v=aQTRebqlvMw -~-~~-~~~-~~-~-