Abstract
The Universal Hardware Data Model (UHDM) [1] Open source project aims at enabling Open source EDA tools to support the entire SystemVerilog 2017 Standard [2]. On one side parsers like Surelog [3] parse and populate the UHDM model and on the other side client tools like Synthesis, Simulation, Linters and so on read back from the compiled model and perform their tasks. Keywords—SystemVerilog 2017, Open Source Parser, Persistent Data Model
Authors
Alain Dargelas [email protected] (Data Model Solutions, LLC)
Henner Zeller [email protected] (Google)
