a21 OpenLANE: The Open-Source Digital ASIC Implementation Flow

Abstract OpenLANE is a tape-out-hardened flow that addresses two main use cases: hardening a macro and integrating a System-on-a-Chip (SoC). It was used successfully to tape out a family of RISC-V based SoCs known as “striVe”. This paper reviews the various components of the flow with a particular focus on the challenges that faced SoC integration while working on the first of the striVe chips and the main ideas used to overcome them, achieving full automation. Authors Ahmed Ghazy [email protected] (eFabless) Mohamed Shalan [email protected] (The American University in Cairo)