AccelerationofComplex RISC-VProcessorVerificationUsingTestGeneration IntegratedwithHardwareEmulation
Simulation performance has long been seen as the bottleneck to design verification. Performance in the thousands of instructions per second, even tens of thousands of instructions per second, makes running long tests on complex designs difficult. However, long tests and complex stimulus are required to put complex processors into interesting states where micro-architectural bugs are more readily found. With RISC-V processors and processing subsystems adding features including custom instructions to support high performance computing (HPC), AI, and automotive use cases among others, verification throughput becomes critical to achieving functional coverage closure. While running software for various use cases is a necessary piece of the verification plan, this does not sufficiently stress the Device Under Test (DUT) and drive it into corner cases. Micro-architectural features such as caches and complex memory transitions are very difficult to verify without long-running, synthetic tests. For example, the simple scenario of filling up a 4MB L3 cache using single byte memory operations needs more than 4 million instructions to execute. Bugs in these micro-architectural areas not only lead to functional issues but may also introduce security vulnerabilities.
