As an import hardware methodology, RTL design flow is strengthened rather than forgotten in Vitis. With a simple and straightforward flow, you can port your existing RTL design or start a new RTL design with Vitis easily and efficiently. This session will show some basic flows to finish the RTL kernel design and integration with Vitis Flow.
00:00 Introduction
00:30 Vitis for Hardware Acceleration
03:37 RTL Kernel Features and Supports in Vitis
12:56 Use RTL Kernel Wizard to Build RTL Kernel
20:24 Use Vivido IP Packager to Build RTL Kernel
27:09 Use Vitis to Verify and Integrate RTK Kernel
29:28 Example Designs for RTL Kernel in Vitis Tutorials
33:13 Summary
