Agile, Reusable, Explainable Methodology for Designing Efficient Next-Gen Hardware Accelerators

[LATTE 22] #5: Design Space Description Language for Automated and Comprehensive Exploration of Next-Gen Hardware Accelerators Abstract: Design space exploration (DSE) of accelerators, especially for machine learning, require efficient hardware/software codesigns that meet strict execution constraints, such as latency, throughput, energy, chip area, power, storage, and task accuracy. The need for a single accelerator for multiple computational workloads necessitates bottom-up exploration. Exploration of accelerators typically involves an architectural template specified in an architecture description language (ADL). So, the design process focuses on a specific architectural organization (i.e., specific types of computational and memory units interconnected in certain ways and hierarchy) -- like defining a systolic array or a spatial architecture (where processing elements share a unified buffer that is filled by DMA transfers). Such an approach can limit the design space that can be explored, the reusability and automation of the full system stack, explainability of obtained outputs, and exploration efficiency (i.e., finding optimal designs in small time). We envision Design Space Description Language (DSDL) for comprehensive, reusable, explainable, and agile DSE. We describe how its flow graph abstraction enables comprehensive DSE of modular architectures, with architectural components organized in various hierarchies and groups. We also discuss full-stack automation, i.e., tools of characterizing, simulating, and programming new architectures. Lastly, we describe how DSDL flow graphs facilitate bottleneck analysis, yielding explainability of the design costs and of design selection during optimization, as well as a super-fast exploration. Skim through a short 2-page paper about this talk: https://mpslab-asu.github.io/publications/papers/Dave2022LATTE.pdf This talk is presented at Second Annual Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE), co-located with ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2022. #computerarchitecture #designautomation #computing #computerorganization #automation #machinelearning #artificialintelligence #computerchips **** Additional Resources: **** - Learn about recent advances in designing accelerators for machine learning in this comprehensive survey: https://arxiv.org/abs/2007.00864 [In Proceedings of the IEEE, 2021]