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Algorithmic Level Techniques for Low Power Design | State Encoding for binary counters, FSMs| Gating

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May 7, 2026
16:48

You will learn how proper state assignment and clock control techniques help in minimizing switching activity and reducing dynamic power dissipation in digital circuits. The concepts are explained in a simple and easy-to-understand manner with a focus on VLSI and ASIC design applications. Topics Covered: Algorithmic Level Low Power Techniques State Encoding for Binary Counters State Encoding for FSMs Clock Gating in FSMs Power Optimization in Digital Circuits 1. Power Dissipation in CMOS: Static, Dynamic, switching, leakage, short circuit power with derivations: https://youtu.be/PTjoqR_AvS0 2. Low Power VLSI Design: Definition, Need, Design techniques-clock gating, Power Gating, Multi voltage: https://youtu.be/aZEBt1a-yUE 3. Low Power VLSI Design Techniques Part-2: Isolation cells and Level Shifter cells: https://youtu.be/UoBf0pUAdCI

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Algorithmic Level Techniques for Low Power Design | State Encoding for binary counters, FSMs| Gating | NatokHD