Artificial Intelligence in ASIC/SOC Verification

Presented at DVCon Europe 2021 Session T1.2 With the ever-increasing complexity and the abundance of data to analyse during debugging, the ASIC /SOC verification engineers are facing the situations where the time consumption for analysis during debug is ranging from hours to days. Major contributor for that is finding out the sweet spot where the issue lies. As no part of the verification environment goes into the chip it has been a practice across verification environment developers not to streamline the testbenches in such a way that it automatically catches the sweet spot. The main hurdle to concentrate in this aspect is that it will be complex and cumbersome effort to identify the sweet spots as there will be multiple protocols involved and the complexity of the protocol also adds to that. The problem is more complex if the debug is at SoC level where the data path is not limited to IPs alone but also includes the processors. Debugging takes long because there are big-data sets to analyse without proper tools. Debugging is a series of questions, assumptions, and conclusions. Traditional debugging flow starts with huge log files from different sources. Writing down the numbers like timestamp and invoked code line numbers from the log files. Dumping the waves to analyse the correctness at each eventful clock cycle. While semiconductor verification techniques have evolved considerably over the last 25 years, the debug of design problems found during verification has barely changed. Since the inception of Hardware Description Languages (HDLs) and simulation we have viewed verification output in the same way we analysed discrete digital circuit cards, through the lens of the logic analyser. It is true that there are new windows on top of the good old-fashioned waveform tool, and the GUI is a bit fancier, but fundamentally we look at tool output, signal-by-signal, one time tick at a time. Verification has changed radically. Designs have grown, leveraging reused intellectual property. Design complexity has also changed with multi-core onboard processing, advanced algorithms, and high-performance communication structures. Simulation has got faster and faster, and given way to emulation and formal verification, with different characteristics in terms of data storage and use models. All these developments have put a strain on the debug tools. Be it efficiently processing large data sets, visualizing complex components, or examining intricate test scenarios, all these activities are harder. This has led to debug occupying more than a third of the total verification effort. The ultimate result of a missed or incorrectly repaired bug is a full fabrication re-spin, at great expense both in terms of money and time. It is time to re-examine the entire debug process and leverage new algorithms and capabilities that may be available to us, but without throwing away the good work performed over the last twenty-five years. New algorithms including Machine Learning, visualization approaches, and problem-solving ideas allow a different approach to debug that saves up to an order of magnitude in debug time. In this tutorial we will be presenting AI concepts and AI concepts applied to verification debug solution. It enables a logical methodology allowing engineers to visualize the essence of data and track down the root cause to problems in an efficient and error-free manner effectively verifying large-scale designs using emulation and regression simulation offering significant improvements right across the verification process. Presenters: Paul Kaunds & Ramesh Yadav, P&C Tech Consultants https://dvcon.org https://dvcon-proceedings.org