Initial result of an FPGA implementation of RISC-V RV32I.
A simple system is put together for a short video demo.
Some modules are reused from a previous FPGA project :
https://youtu.be/G4Mo5UtstFY
Software tool used for this project :
https://xpack.github.io/blog/2021/11/11/riscv-none-embed-gcc-v10-2-0-1-2-released/
