In this video of the Cadence Tutorial series, I continue from the previous session where we designed the schematic of an inverter. Here, I demonstrate how to:
Simulate propagation delay
Analyze noise margins (NML & NMH)
Equalize the noise margin by setting VM = VDD/2
This tutorial is helpful for VLSI beginners, students, and anyone learning analog/digital circuit design using Cadence Virtuoso.
📌 Topics Covered:
Inverter simulation in Cadence
Measuring propagation delay
Noise margin calculation (NML & NMH)
Balancing noise margins for reliable design
Don’t forget to check the previous video where I designed the inverter schematic.
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