CDC Reset Path: Why De-assertion Causes Metastability

Most engineers know asynchronous resets are dangerous — but do you know why only de-assertion causes metastability and not assertion? This is a classic CDC interview trap. Get it wrong, and your reset synchronizer fails in silicon. In this video, we do a deep dive into CDC Reset Path behavior — breaking down exactly what happens when a reset signal generated in CLKA domain is applied to a flip-flop clocked by CLKB, and why de-assertion is the critical path that demands synchronization. 🔍 What You Will Learn: Why reset assertion is independent of the clock and causes no metastability Why reset de-assertion can violate setup/hold time of CLKB — and trigger metastability How an asynchronous active-low reset behaves across clock domains The correct approach: synchronizing reset de-assertion using a multi-flop synchronizer in the destination domain (CLKB) How to reason about CDC reset paths in RTL reviews and timing sign-off 🎯 Common Interview Questions Covered: "What is the difference between reset assertion and de-assertion in CDC?" "Why do we synchronize reset de-assertion but not assertion?" "What happens if an asynchronous reset de-asserts near the CLKB edge?" "How do you design a reset synchronizer for a CDC path?" ▶ Clock Domain Crossing — Full Series📌 Topics Covered: Clock Domain Crossing (CDC) | CDC Reset Path | Reset Metastability | Asynchronous Reset | Reset De-assertion | Reset Synchronizer | VLSI Interview Prep | Static Timing Analysis | RTL Design | Synopsys Design Constraints | Physical Design Interview | Semiconductor Design🚀 vlsideepdive — Bridging VLSI theory and industry practice for engineers who want to go deeper.