Charge sharing between two capacitors

When we have two capacitors, Cs and Cb, with initial voltage levels Vs and Vb respectively, and we close the switches to share charge between them, the following occurs: 1. **Voltage Level Equalization**: Charge sharing ensures that the voltage levels of the two capacitors become equal. Let's denote these final voltage levels as Vs and Vb. 2. **Charge Conservation**: According to the charge conservation law, the total charge remains constant during this process. For example: - If Cs is 5 femtofarads, Cb is 20 femtofarads, Vs is 1 volt, and Vb is 0.5 volts initially, after closing the switch, both capacitors will stabilize at a final voltage of 0.6 volts due to charge sharing. - In another scenario with Cs and Cb having the same capacitance but with initial voltage levels of 0 volts for Cs and 0.5 volts for Cb, the final voltages will be 0.4 volts after charge sharing. DRAM utilizes this phenomenon in its operation, with an NMOS transistor acting as an access transistor serving the role of a switch. The gate of the transistor is connected to the word line, and the drain is linked to the bit line, forming the basic structure of a DRAM cell. Various voltage levels associated with a DRAM cell include: - Word line turn-on voltage (Vpp) at 2.9 volts. - Word line turn-off voltage (Vnwl) at -0.3 volts. - Bit line precharge voltage (VbIp) at 0.5 volts. - Cell plate voltage of the storage capacitor (Vcp) at 0.5 volts. - VDD level for DDR4 at 1.2 volts, with V-array at 1.0 volt. In modern DRAM design, achieving reasonable charge sharing results involves considerations such as Cs and Cb values, where Cs is typically around 5 femtofarads. The balance between chip size and optimizing Cs and Cb values is crucial, with a preference for larger Cs and smaller Cb for efficient operation. As DRAM technology advances, there is a trend towards increasing the number of cells per bit line to enhance memory performance and efficiency.