Chapters
0:00 Quick Glassdoor Question
1:27 FSM Modulo Problem In Verilog
13:24 Testing & Debugging
Ahh, streaming bits and seeing if it's divisible by stuff. Classic interview question.
In this Verilog interview question, I walk through my process of writing a Verilog solution (via FSM, or 'finite state machine') to see if a number is divisible by 5 given an input that's supposed to represent a bit being pushed into the least-significant bit.
In the testbench, I generate a decimal variable which allows me, to at a glance, use ninja hacks, to know if a number is divisible by 5. Here's a song teaching you how to employ this hack: https://www.youtube.com/watch?v=7VjcUOmPS5k&ab_channel=uschronicle
