Clock Gating & Pulse Width Checks (STA Ep. 3)

Most students master Setup and Hold, but do you know what happens when a Reset signal hits at the wrong time? In this video, we go beyond the basics to explore the advanced Static Timing Analysis (STA) checks—Recovery, Removal, Clock Gating, and Pulse Width—that are critical for clearing VLSI interviews and ensuring your chip actually works. We explain why "Recovery" is essentially the Setup check for asynchronous signals, and why failing a Clock Gating check can cause glitchy clocks that destroy functionality. In this video, you will learn: Clock Gating Checks: How to verify enable signals to prevent clock clipping and glitches. Recovery Time: The minimum time an asynchronous signal (like reset) must be stable before the active clock edge. Removal Time: The minimum time an asynchronous signal must remain active after the clock edge to prevent metastability. Min Pulse Width: Ensuring high/low signal phases are wide enough for standard cells to operate correctly. Watch the previous episode first: 👉 Setup & Hold Slack Calculation Made Easy | STA Ep. 02: Watch Ep. 02 Here - https://www.youtube.com/watch?v=5ehl1fMei8w Timecodes: 0:00 - Introduction to Advanced STA Checks 2:58 - Slew/Transition Analysis? 5:14 - Clock Skew Analysis 8:09 - Pulse Width Checks Let's connect online 👨🏻‍💻 LinkedIn: https://www.linkedin.com/in/vikas-sachdeva-vlsi/ #VLSI #StaticTimingAnalysis #ElectronicsEngineering #Semiconductors #STAchecks #DigitalDesign