This is a preview of the course for learning randomized functional coverage with the UVVM VHDL verification framework.
Click here to read more and see how to access this course:
https://vhdlwhiz.com/product/course-functional-coverage-driven-vhdl-testbench-using-uvvm/
This course teaches how to create self-checking VHDL testbenches that use advanced randomized testing strategies to verify VHDL designs.
We use the free and open-source Universal VHDL Verification Methodology (UVVM) framework and a free version of the Questa simulator to check a device under test (DUT) from the VHDLwhiz library.
Constrained random verification (CRV) is a method that relies on letting the testbench randomly interact with the device under test. Then, based on specific constraints or limits, the testbench decides which stimuli to use and when to stop.
In this course, we implement a CRV-based testbench using UVVM features like bus functional models (BFMs /VVCs), intelligent randomization, scoreboards, and logging and checking functions.
You will learn to set up coverage points to monitor the DUT during simulation and sample hits in “bins” to ensure 100% functional coverage of events you want to test in your VHDL code.
