Doulos KnowHow Tips - Static Vs. Automatic Variables

In this Doulos KnowHow tip, Doulos certified instructor Brian Jensen reviews the usage of static and automatic variables in System Verilog, before simulating an example in EDA Playground. This is an excerpt from the Doulos ON-DEMAND webinar Common Mistakes in SystemVerilog, which you can view in full by registering here: https://bit.ly/42bf0zI Doulos provides scheduled classes online and in-person & delivers on-site team-based training & interactive online learning events worldwide – you can find out the very latest on our website: https://www.doulos.com POPULAR SystemVerilog TRAINING SystemVerilog for New Designers: https://bit.ly/3S9H0PJ Comprehensive SystemVerilog: https://bit.ly/47HIJS4 To enquire about training for you, or for your team: https://bit.ly/4bPuttj Subscribe to our channel, @DoulosTraining, for more: - Introductory videos to range of our most popular training topics – System Verilog, UVM, SystemC & TLM-2.0, VHDL, Python & Deep Learning, & Arm. - Answers to common questions & “how to’s ”. - Our latest live & on-demand webinars (& joining links). Subscribe (and set your notifications): https://bit.ly/3MYWzsk Follow us on Twitter: @DoulosTraining Follow us on LinkedIn: https://uk.linkedin.com/company/doulos-ltd #DoulosOnDemand #SystemVerilog #CommonMistakesInSystemVerilog