DRAM array structure and read write operation

DRAM array structurs are like following. 1. Components and Their Functions: MAT (Memory Array Tile): The fundamental unit of storage in the DRAM array. It consists of multiple memory cells organized in rows and columns. SWD (Sub Word Line Driver): Responsible for driving the word lines within a specific section or segment of the memory array. SWC (Sub Word Line Control): Manages the control signals for the SWD, ensuring proper selection and timing. BLSA (Bit Line Sense Amplifier): Amplifies the small differential voltage on the bit lines (BL, BLB) during read operations to determine the stored data. 2. Page Size: Page Size refers to the number of memory cells connected to one word line. This size is defined by JEDEC standards and varies depending on the DRAM chip design. 3. Cells Per Bit Line: The number of cells connected to each bit line is crucial for determining the density and performance of the DRAM. Common values are 688, 832, 928, etc. The number of cells per bit line is influenced by the design parameters, such as the ratio of Cb and Cs ratio. 4. Data Write Operation: Strong IO Driver: Drives the GIO, GIOB lines to the LSA (Line Sense Amplifier) NMOS transistors. These in turn drive the LIO, LIOB lines and through the CSL (Column Select Line) drive the bit lines (BL, BLB). During a write operation, the strong IO driver needs to overcome the BLSA. Since BLSA is not very strong, it is easier to flip the BLSA and write the data into the memory cells. 5. Data Read Operation: BLSA: During a read operation, the bit line sense amplifier is relatively weak compared to the strong IO driver. It has to drive the LIO, LIOB lines to a sense amplifier (IOSA). Sense Amplifier (IOSA): This component is essential because the BLSA cannot fully drive the IO lines due to their heavy loading. Instead, the IOSA amplifies the small voltage changes on the bit lines to accurately determine the stored data. 6. Precharge Levels: GIO, GIOB: Precharged to VDD (the full supply voltage). This ensures that during read operations, the voltage levels are stable and can be accurately sensed. LIO, LIOB: Initially Precharged to Half VDD. When the memory section is selected, the voltage level changes to VARY. This variation allows the sense amplifier to detect differences and determine the stored data. Summary: Write Operation: Strong IO drivers directly write to memory cells, overcoming BLSA. Read Operation: Weak BLSA, due to heavy loading on IO lines, needs assistance from IOSA to amplify voltage changes for accurate data sensing. This detailed description covers the key components and their interactions in a DRAM array, focusing on the roles they play during read and write operations and how voltage levels are managed during these processes.