DRAM Latency control scheme

As DRAM generations have evolved, clock speeds have also doubled. For DDR1, the positions of the P-clock and DLL-clock may not be reversed. However, starting from DDR2, due to the faster clock speeds compared to DDR1, the tCK becomes smaller than Td-out. As a result, the DLL-clock is ahead of the P-clock. In DDR3, the DLL-clock can be more than two clock cycles ahead, with its position varying depending on the process, voltage, and temperature (PVT) conditions. The read command is decoded by the P-clock, but the clock domain must be switched to the DLL-clock because the output driver is gated by the DLL-clock. To address this issue, a new approach is introduced. By utilizing two ring counters—one controlled by the DLL-clock and the other by the P-clock—the system can automatically latch and transfer the read command, leveraging the relationship between the P-clock and DLL-clock.