DVD - Lecture 2e: Coding Style for RTL - part 1

Bar-Ilan University 83-612: Digital VLSI Design This is Lecture 2 of the Digital VLSI Design course at Bar-Ilan University. In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS). Lecture 2 overviews the Verilog Hardware Description Language and provides coding style guidelines for writing synthesizable register transfer level (RTL) code. Lecture 2e emphasizes some of the important points for coding in Verilog in order to write synthesizable, maintainable code. Lecture slides can be found on the EnICS Labs web site at: https://enicslabs.com/academic-courses/dvd-english/ All rights reserved: Prof. Adam Teman Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs Faculty of Engineering, Bar-Ilan University