Bar-Ilan University 83-612: Digital VLSI Design
This is Lecture 4 of the Digital VLSI Design course at Bar-Ilan University. In this course, I cover the basics of Chip Implementation, from designing the logic (RTL) to providing a layout ready for fabrication (GDS).
Lecture 4 continues the discussion about logic synthesis, focusing on the algorithms and mechanics that enable logic synthesis and timing optimization.
Lecture 4c very briefly introduces constraint definition. A full blown discussion of timing constraints and the SDC format are given in Lecture 5.
Lecture slides can be found on the EnICS Labs web site at:
https://enicslabs.com/academic-courses/dvd-english/
All rights reserved:
Dr. Adam Teman
Emerging nanoscaled Integrated Circuits and Systems (EnICS) Labs
Faculty of Engineering, Bar-Ilan University
