ECE 165 - Lecture 7: Layout and Combinational Logic I (2021)

Lecture 7 in UCSD's Digital Integrated Circuit Design class. Here we introduce the basics of doing layout - or physical design - in modern CMOS processes. We use an open-source 45nm PDK in this example. With this understanding of layout, we then introduce techniques to help improve the speed of designs through input ordering, asymmetric gates, skewed gates, and combinational path optimizations. We conclude with a rule-of-thumb for fan-in and fan-out.