EDA Tools Tutorial Series - Part 9: Active-HDL

In this tutorial, we explore FSM (Finite State Machine) design using Active-HDL. This session demonstrates two approaches: Drag-and-Drop FSM Design – A visual way to create FSMs easily. Block Diagram Approach – Structuring testbench for FSMs test We take a 1011 Sequence Detector as an example and: Design the FSM step-by-step. Implement & simulate using Active-HDL. Create a testbench to verify functionality. FSM basics & design in Active-HDL Drag-and-drop approach for FSM creation Block diagram approach for FSM test setup implementation Running simulations & verifying output Like, Share & Subscribe for more EDA tutorials! #ActiveHDL #FSM #EDATools #VLSI #Verilog #SequenceDetector #HDL #Simulation