DSPAA Module 2 Class 6
Speed Issues
Hardware Architecture
MAC Implementation
Single MAC Implementation of 8-Tap (coefficient ) FIR Filter
Pipeline Implementation
Parallel Implementation of FIR Filter
00:00 Intro
00:20 Topics covered
00:33 Speed issues
01:10 Hardware architecture
01:55 Parallelism
04:18 Pipelining
07:13 System Level Parallelism and Pipelining
07:57 Implementation of 8-Tap (coefficient ) FIR Filter using Single MAC
09:36 Pipeline Implementation
11:35 Parallel Implementation of FIR Filter
14:46 Summary of different Implementation
15:55 Features for external interfacing
