How do you program an FPGA? What does the concepts even mean? How do FPGA programming languages differ from software programming languages? These are the questions we'll tackle in this series.
The fourth part deals with timing considerations. How do you know whether your design is fast enough to handle the load, and what does that even mean?
I want to thank all of my Patreaon supporters, and especially my BBC Micro level supporters:
Yehuda T. Deutsch
Support the project on Patreon: https://patreon.com/CompuSar
We also have a Discord server. You can join it by following the following link: https://discord.gg/nNv53PWgBj
Table of contents:
00:00 - Simple circuit
00:59 - Propagation delay
07:31 - Setup and Hold Time
10:32 - No timing analysis
16:37 - Defining a clock
19:34 - Slack, WNS and TNS
21:21 - Decreasing the slack
23:24 - Faster clock
26:07 - Using a violating design
27:29 - Why does it work?
