In this video, we'll see the main properties of the "module" in Verilog and create the 'gate level' design and simulation code for a 4x1 Mux in Vivado Design Suite. Finally we'll be running the simulation and observing the behaviour of our design.
0:00 Introduction
0:17 'module' definition & contents
1:35 Design Verilog Code for 4x1 Mux
3:30 Simulation Code
5:51 Vivado Design Suite Implementation
