GATE PYQs on Direct Cache Mapping || GATE CS 2011 and 2015 Question on Direct Cache Mapping

#GATECS #PYQs # DirectCacheMapping #GATEcs2011#GATEcs2015 GATE PYQs on Direct Cache Mapping GATE CS 2011 Question on Direct Cache Mapping An 8KB direct-mapped write-back cache is organized as multiple blocks, each of size 32-bytes. The processor generates 32-bit addresses. The cache controller maintains the tag information for each cache block comprising of the following.1 Valid bit1 Modified bitAs many bits as the minimum needed to identify the memory block mapped in the cache. What is the total size of memory needed at the cache controller to store meta-data (tags) for the cache? GATE CS 2015 Question on Direct Cache Mapping Consider a machine with a byte addressable main memory of 220 bytes, block size of 16 bytes and a direct mapped cache having 212 cache lines. Let the addresses of two consecutive bytes in main memory be (E201F)16 and (E2020)16. What are the tag and cache line address (in hex) for main memory address (E201F)16?