GPU: L3 Part 1: CUDA Synchronization

CHEKKALA SANDEEP REDDY: NO srikakolapu bhagavan: no sir R Sowmeya Lakshmi: No Ponnampalam Pirapuraj: no Chinmay Rajesh Ingle: T2 while condition becomes true if initially flag is Soumik Basu: If you think in assembly level, both can work in parallel. Soumik Basu: As T1 before writing can context switch and T2 can go inside and then T1 context switches back Chinmay Rajesh Ingle: yes Soumik Basu: yes Chinmay Rajesh Ingle: after we are in loop for T2 we switch to T1 which makes the flag 1 and we enter into T1's loop CHEKKALA SANDEEP REDDY: T1 may loop infinitely and S1 may not excute always CHEKKALA SANDEEP REDDY: NO, if no cache coherence problem Ponnampalam Pirapuraj: no Abhishek u: Can cache coherence issue be seen by the programmer? Chinmay Rajesh Ingle: in assembly level we may read and other(2nd process after context switch) one would have updated till the time we are checking condition on the flag for the 1st process Chinmay Rajesh Ingle: same thing you mentioned VIPIN PATEL: If the flag variable is allocated in the register then both cores may see different values of the flag, as registers are out of the scope of cache coherence protocol. Ponnampalam Pirapuraj: no CHEKKALA SANDEEP REDDY: Yes, flag = 1, flag = Abhishek u: yes on flag VIPIN PATEL: Yes on flag variable srikakolapu bhagavan: yes Prajwal Kumar A: yes CHEKKALA SANDEEP REDDY: no CHEKKALA SANDEEP REDDY: T1 may hang irrespective of intial flag value Shubham K Vyas ae18d Shubham K Vyas ae18d CHEKKALA SANDEEP REDDY: YES YES Shubham K Vyas ae18d Rupesh Nasre IITM: if (grade[tid] == 'U') countU++; CHEKKALA SANDEEP REDDY: countU should be added atomically Abhishek u: updates to count may be lost CHEKKALA SANDEEP REDDY: yes for node C CHEKKALA SANDEEP REDDY: yes Varun Gupta: yes srikakolapu bhagavan: yes sir Ponnampalam Pirapuraj: yes VIPIN PATEL: no question Rupesh Nasre IITM: https://github.com/gramoli/synchrobench/tree/master/c-cpp/src Soumik Basu: ensures mutual Exclusion but does not allow anyone to move ahead. order will be based on inital value of flag CHEKKALA SANDEEP REDDY: NO VIPIN PATEL: it enforces ordering on execution of T1 and T1 VIPIN PATEL: *T2 R Sowmeya Lakshmi: initial value matters Abhishek u: sir, flag is volatile is not required for sequential consistency, because each threads a committed value. CHEKKALA SANDEEP REDDY: two may loop infinitely Abhishek u: *reads Soumik Basu: two may lock but may not unlock VIPIN PATEL: both thread can deadlock CHEKKALA SANDEEP REDDY: NO srikakolapu bhagavan: both won't be simultaneously Soumik Basu: is flag always false initially ? VIPIN PATEL: flag value will be overwritten so initial value does not matter CHEKKALA SANDEEP REDDY: YES CHEKKALA SANDEEP REDDY: Does volatile means value is committed. Soumik Basu: If we can gurantee that two threads will share a common cache then we can save some time by removing volatile ? It is not possible in compile time but can be possible in run time ?