GRE Computer Science Question 56

56. Consider a single-issue processor with an in-order five-stage pipeline (IF, ID, EX, MEM, and WB) and with the following characteristics. • The register file can be written and then read in the same cycle. • The pipeline does not have other bypassing/forwarding hardware. • Instructions, including loads and stores, spend only one cycle in the MEM stage. Consider the following MIPS-like instructions in which the destination register is the first (leftmost) register. The instruction set supports (i) register-indirect addressing, which is indicated by using parentheses and (ii) displacement addressing, which is indicated as an integer offset from a register indirect value. loadword $t0, ($t1) add $t2, $t2, $t0 loadword $t0, 4($t1) add $t1, $t1, 1 add $t2, $t2, $t0 sub $t3, $t1, $t0 How many stall cycles do the instructions incur? (A) 0 (B) 1 (C) 2 (D) 3 (E) 4