How to Simulate and Test SystemVerilog with ModelSim (SystemVerilog Tutorial #2)

In this video I show how to simulate SystemVerilog and create a testbench. Video 1 (How to Write an FSM in SystemVerilog): https://www.youtube.com/watch?v=ENH-8zZLbK8 Video 3 (How to Write a SystemVerilog TestBench): https://www.youtube.com/watch?v=Hu9V0_ffp30