How to use a While-Loop in VHDL

Learn how to increment a variable in a loop while its value is less than a certain number. The While-Loop is one of the most versatile loops in the VHDL language. It’s often used when we want to test an expression before each iteration of the loop, rather than iterating a predefined number of times. Blog post for this video: https://vhdlwhiz.com/while-loop/ The syntax of the While-Loop is: while [condition] loop [code to loop over] end loop; The condition must be either “true” or “false”, but it can also be an expression that evaluates to true or false. This is an example expression which evaluates to true if “i” is equal to 5: i = 5 Or this example which evaluates to true whenever “i” is not 0: i /= 0 Before each iteration, the While-Loop will test the condition. If it is true, the While-Loop will iterate once more, if it is false, it will terminate. Variables in VHDL are usually declared in the declarative region of the process. The syntax of a variable declaration is: variable [name] : [type] := [initial_value]; The initial value is optional. To assign to a variable we need to use the “:=” operator, just like in the variable declaration.