Image processing on FPGA using Verilog HDL

This FPGA project is aimed to show in details how to process an image using Verilog from reading an input bitmap image (.bmp) in Verilog, processing and writing the processed result to an output bitmap image in Verilog. In this FPGA Verilog project, some simple processing operations are implemented in Verilog such as inversion, brightness control and threshold operations. The image processing operation is selected by a file and then, the processed image data are written to a bitmap image for verification purposes. The image reading Verilog code operates as a Verilog model of an image sensor/ camera, which can be really helpful for functional verifications in real-time FPGA image processing projects. The image writing part is also extremely useful for testing as well when you want to see the output image in BMP format. Here I have given the Matlab and Verilog codes. Click on this link: https://drive.google.com/drive/folders/1g9K18hUtLdPtl6mUUW5cqOyOzQquwvwj?usp=sharing