This video explains how to write VHDL code for a Half Adder using dataflow, behavioral, and structural modeling. It gives you more insight on structural modeling, component declaration, and component instantiation.
01:01 Half Adder Using Dataflow/Concurrent Modeling
03:28 Half Adder Using Behavioral Modeling
07:09 Half Adder Using Structural Modeling
Previous videos
Create new project in Vivado, Simulate & implement logic gates on FPGA - https://youtu.be/Dld3rW6vEPk
#VHDL - Introduction, Terms, Styles of Modelling, Component Instantiation - https://youtu.be/c6b1W7wu6po
#Vivado - Download, Installation, and Licensing - https://youtu.be/b1m3SbFrTDI
FPGA Basics - https://youtu.be/RnXK0n0grmc
Install Vivado board files for Basys 3, Nexys 4, Arty, Genesys 2, Zybo, and Zedboard - https://youtu.be/24slpAxjCmM
#Xilinx #HalfAdder
Thanks,
Abhyaas Training Institute
Contact - [email protected]
