This lecture covers the following.
- Contamination and propagation delay in combinational logic
- Timing diagram for a latch
- Timing diagram for a flipflop
- Setup time, hold time
- Latch implementation using a MUX
- Latch implementation using a bistable element
- Flipflop implementation using master-slave configuration
EE619A: VLSI system design (2023)
Instructor: Chithra ( https://home.iitk.ac.in/~chithra )
MVLSI, EE, IIT Kanpur
For more lectures on other topics from our lab, you may visit https://www.iitk.ac.in/sscd/Teaching.html
