Logic Synthesis flow | RTL Synthesis flow | RTL2GDS | Design Compiler (DC) tutorial

Logic Synthesis is performed once the RTL code is simulated and verified. In Logic Synthesis, A RTL code is converted into a gate-level netlist of given standard cell library. Logic Synthesis Flow using DC (Design Compiler of Synopsys) has been explained in this tutorial. In this RTL-to-GDSII flow of video series, there is a total of 10 sessions. We have covered all the stages of ASIC design using EDA tools demonstration and also the basic theories. Part-wise descriptions of the different session and the link of videos are as follow. 1. Session-1: Overview of RTL to GDSII flow | Basic terms in the flow Video link: https://youtu.be/THXPuNNdPqw 2. Session-2: Flow in EDA tool's perspective | Different EDA tools | various files Video link: https://youtu.be/S4Yzexeq3l8 3. Session-3: Functional verification of RTL | using Synopsys VCS | VCS demo Video link: https://youtu.be/RDtGyHfP_eQ 4. Session-4: Logic Synthesis flow | RTL to gate-level netlist | Design compiler Video link: https://youtu.be/tLVAyfTfTNY 5. Session-5: Logic Synthesis | Design Compiler | Command-line | gate level netlist Video link: https://youtu.be/sIDe76QFG2g 6. Session-6: Logic Synthesis | Design Compiler | GUI Mode| design_vision Video link: https://youtu.be/N3CCQmcX3fk 7. Session-7: Logic Equivalence Check using Formality |S8| RTL-to-GDSII flow | Formality tutorial Video link: https://youtu.be/CFRqPnqifx0 8. Session-8: Physical Design Flow | PnR flow |RTL-to-GDSII flow | innovus flow Video link: https://youtu.be/1kLUdi0qNBo 9. Session-9: Design Import | Physical Design |RTL-to-GDSII flow | innovus tools tutorial Video link:https://youtu.be/OMhTtqnzDOA 10.Session-10: Place and Route in Cadence Innovus | full PnR flow | Cadence Innovus demo Video link: https://youtu.be/TDvq1hVXzRc ====Connect with us========================== All on one page: https://www.teamvlsi.com/p/contact_8.html Blog: https://www.teamvlsi.com Facebook Page: https://www.facebook.com/teamvlsi WhatsApp Group: https://chat.whatsapp.com/C6etLHR6oAf6G9bLGDwdOf Telegram Group: https://t.me/teamvlsi (Or search team VLSI on telegram) Email: [email protected] ============================== #LogicSynthesis #DesignCompiler #LogicSynthesisFlow