Memory Design and Test - Session 19

This video (0:00 - 1:01:10) covers the design challenges of DRAM, specifically focusing on leakage current, capacitor size, and memory organization. It details how DRAM differs from SRAM, highlighting the need for periodic refreshing due to volatile charge storage. The lecture explains the square array organization (6:32) used in DRAM to minimize the address bus width and simplify decoding logic. It also emphasizes the importance of storing only one bit per word within an array to enhance error correction efficiency against high-energy particles (11:05). The final portion discusses timing protocols to optimize performance, including RAS (Row Address Strobe) (13:35), CAS (Column Address Strobe) (13:47), and burst mode (25:32) to improve data throughput. Bandwidth calculations are illustrated with a practical example (55:13). Video Chapters: Introduction to DRAM Challenges (0:00 - 2:00) Leakage and Refresh Requirements (2:00 - 5:10) Capacitor Design Considerations (5:10 - 6:30) Square Array Organization and Addressing (6:30 - 10:45) Error Correction and Memory Structure (10:45 - 13:30) RAS and CAS Signals (13:30 - 16:55) Data Read Process and Latency (16:55 - 20:50) DRAM Timing (TRAC, TRC, TCAS) (23:40 - 25:30) Burst Mode Access (25:30 - 26:30) Early vs. Late Read/Write Cycles (26:30 - 34:00) Refresh Cycles and Bandwidth (34:00 - 55:10) Bandwidth Calculation Example (55:10 - 1:01:10)