mipi protocol part1

MIPI CSI-2 (Camera Serial Interface-2) is a high-speed, low-power interface used to transfer image data from a camera sensor to a host processor, organized in layered architecture including application, pixel/byte packing, protocol (packetization), low-level protocol, lane management, and PHY layers; image data is packetized with headers (data type, virtual channel, word count), payload, and ECC/CRC for reliable transmission across multiple lanes. At the physical layer, two main options exist: D-PHY and C-PHY. D-PHY uses differential signaling with a dedicated clock lane and separate data lanes, operating in high-speed (HS) mode for data transfer and low-power (LP) mode for control, making it simpler and widely adopted with straightforward timing and lane scaling. In contrast, C-PHY uses 3-wire “trios” with embedded clock encoding (no separate clock lane), achieving higher bandwidth efficiency per wire and better EMI performance, but with more complex encoding/decoding (symbol-based transmission like 16/7 or 24/7 encoding). The key difference is that D-PHY relies on explicit clocked differential pairs while C-PHY embeds clock within data using fewer wires for higher efficiency. For control, CSI-2 systems use CCI (Camera Control Interface), an I²C-compatible protocol where the host (master) reads/writes sensor registers (slave); write operations involve sending a slave address, register index (sub-address), and data bytes (MSB first), typically updating multi-byte registers only after the final byte is received, while read operations use a write of the register index followed by a repeated start and read sequence, supporting single or sequential reads with auto-incremented register addressing; to maintain data consistency in multi-byte accesses, buffering mechanisms ensure atomic reads/writes and prevent corruption from partial updates.