Modifying the block design to interface Pmod LCD

Module 1 - Video 5 -- Lab 3 of the course Building an Embedded System on FPGA Link to complete playlist: https://www.youtube.com/playlist?list=PL6jYIySXv7VhUjg95oP88ubxRrr9MQMfH Overview: Modifying the block design to add AXI GPIOs to interface character LCD Topics Covered: 1. Adding AXI GPIOs to the Block Design 2. Connecting the AXI GPIOs to AXI Interconnect 3. Making the ports external and modifying the constraints file 4. Generating the new bitstream and exporting the new hardware 5. Writing code in Xilinx SDK to verify the modified design Resources: Code: https://drive.google.com/file/d/1sWOpiNM-LB4mUAdZtCzxw_YRHUzpgTCM/view For any queries, Email: [email protected]