Reducing Initiation Interval in HLS -- Part 06

Pipelining loops is one of the main optimisation techniques in High-Level Synthesis (HLS). The main parameter in loop pipelining is the initiation interval (II), which determines the number of clock cycles between two iterations of a pipelined loop. In this video series, I take an example and explain how to modify the code to improve the initiation interval. If you have any particular accelerator code, you can leave that in the comments, and I will try to optimise your code and explain that in a video. Udemy Courses Link: https://highlevel-synthesis.com/2021/03/29/high-level-synthesis-for-fpga-online-courses-coupons/ Code on GitHub: https://github.com/highlevelsynthesis/ReducingIIinHLS/tree/main/ReducingIIinHLS-06