Risc-V Single Cycle CPU in Logisim Evolution

This is my submission for a final project for my computer architecture class. It is a culmination of all the labs previous and includes both of my last two videos. I spent a lot of time on this and had help from my partner. Websites used in video: https://www.cs.sfu.ca/~ashriram/Courses/CS295/assets/notebooks/RISCV/RISCV_CARD.pdf https://risc-v-cpu-visualizer.vercel.app/