RiscV Logisim Load Datapath

Learn about the RISC-V instruction set architecture by building hardware. In this video, I add load instructions to the datapath in order to load bytes, half words, and words into the register file. I highly recommend you watch the videos on this playlist to this point as I use many of the modules built to date: https://www.youtube.com/watch?v=Z7LHCMTc0gI&list=PLM8YDhk_PWu0pdBNHMMSiBm8CEkCQ94T8&pp=gAQBiAQB There are a number of resources that I recommend you study as you go on this journey with me: Github for Python Source: https://github.com/chuckb/rv32icltrom/tree/load-datapath RISC-V Reference Card: https://www.cs.sfu.ca/~ashriram/Courses/CS295/assets/notebooks/RISCV/RISCV_GREEN_CARD.pdf Design of the RISC-V Instruction Set Architecture: https://digitalassets.lib.berkeley.edu/techreports/ucb/text/EECS-2016-1.pdf Great Ideas in Computer Architecture (week 2 and 4): https://inst.eecs.berkeley.edu/~cs61c/su18/ RISC-V Specification: https://riscv.org/wp-content/uploads/2019/12/riscv-spec-20191213.pdf Truth Table: https://docs.google.com/spreadsheets/d/1y5XL_3o2Y_Wu3DvEYTaD73T4FT2XFZb02rPnqCzduvI/edit?usp=sharing Other helpful resources: Online RISC-V assembler: https://riscvasm.lucasteske.dev Logisim Evolution: https://github.com/logisim-evolution/logisim-evolution/releases