Synchronous Reset Asynchronous Reset in Sequential design with verilog code

Synchronous and Asynchronous Reset is a very important concept for interviews of VLSI jobs. Clock and reset are synchronous in Synchronous Reset design and reset us Not in sync with clock in asynchronous design. this video clearly explains the concept with example verilog code and waveform for Synchronous and asynchronous reset using d flipflop. Follow @exploreelectronics for Basics 👉 Digital Electronics : https://youtube.com/playlist?list=PLu7-Sp50sShc9KYyj_zesavElCIuh4UME&si=JW2n3FjKcI7Bywnk 👉 Verilog HDL Basics : https://youtube.com/playlist?list=PLu7-Sp50sSheu-zqoq6LkvsJKhH-ro9xs&si=Nulf6e18bwgJp5l- 👉 CMOS VLSI Design : https://youtube.com/playlist?list=PLu7-Sp50sShcF5r4l-FMYxnjlQOsVbN6U&si=iSr9bNWOAHtTkVvo 👉 Whatsapp Channel : https://whatsapp.com/channel/0029Va4waE196H4UrnIX620O 👉 Telegram : https://t.me/explore_electronics #synchronous #asynchronous #reset #clock #sequential #vlsijobs #rtl #interview