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Synthesis Flow

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Jan 19, 2020
55:11

If you wish to support me: https://www.buymeacoffee.com/narashimaraja In this video, we will learn how to perform functional verification for RTL code and then how to synthesis the verified RTL to gate-level netlist using standard library built earlier and a very basic constraint file. We will also learn how to perform functional verification on the gate-level netlist. The functional verification is done using nclaunch tool and Synthesis is done using RTL compiler from Cadence.

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Synthesis Flow | NatokHD