System Verilog Constraint Interview Question

💡 Interview Question: Can you write a System Verilog Write a constraint such that in the following code, all the even numbers from dynamic array arr1 must be stored inside the dynamic array arr2. Assume that arr1 can have any number of elements but not more than 20, and all elements must be greater than 0 and less than 1000. #vlsi #systemverilog #interviewquestions #system Verilog constraint