System Verilog: Sequential Logic and D-Type FlipFlops

This video explains the basics of sequential synchronous logic and how to describe a D-Type Flip Flop in Verilog. Exercise page: https://github.com/STFleming/sv-tute/tree/main/lessons/6-D_type_flip_flop Part of the Swansea University EmSys course: https://github.com/STFleming/EmSys