This video demonstrates my EE178 Lab 3 project: a time-multiplexed quad seven-segment display using Verilog on the Real Digital Blackboard FPGA.
The design uses the 100 MHz onboard clock and four 4-bit input values: val3, val2, val1, and val0. The circuit controls the active-low anode signals and seven-segment signals to display four hexadecimal digits from 0 to F.
The purpose of this lab is to practice digital logic design using counters, multiplexers, decoders, and seven-segment display control. The display uses time multiplexing so each digit can show a different value while appearing to be on at the same time.
Tools used:
- Verilog HDL
- Vivado
- Real Digital Blackboard FPGA
- Quad seven-segment display
Student: Quoc Binh Van & Alan Ton
Course: EE178
Lab: Laboratory Assignment #3
