Universal Shift Register

If the flip‐flop outputs of a shift register are accessible, then information entered serially by shifting can be taken out in parallel from the outputs of the flip‐flops. If a parallel load capability is added to a shift register, then data entered in parallel can be taken out in serial fashion by shifting the data stored in the register. Some shift registers provide the necessary input and output terminals for parallel transfer. They may also have both shift‐right and shift‐left capabilities. The most general shift register has the following capabilities: A clear control to clear the register to 0. A clock input to synchronize the operations. A shift‐right control to enable the shift‐right operation and the serial input and output lines associated with the shift right. A shift‐left control to enable the shift‐left operation and the serial input and output lines associated with the shift left. A parallel‐load control to enable a parallel transfer and the n input lines associated with the parallel transfer. n parallel output lines. A control state that leaves the information in the register unchanged in response to the clock. Other shift registers may have only some of the preceding functions, with at least one shift operation.