UVM IVC generation

Watch VoskenAI generate a complete UVM Interface Verification Component for AXI4-Stream — directly from the ARM IHI0051A protocol specification PDF. No SystemVerilog hand-written. Twenty-two files generated. One self-healed protocol violation. Verilator-clean. This is an unedited demo of the /vos_uvm_architect agent, end to end: PDF input, automated spec build, IVC code generation, Verilator lint, full simulation, protocol-check failure, automated revise sub-agent, re-simulation, PASS — followed by a code tour of the actual generated SystemVerilog. ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━ CHAPTERS ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━ PART 1 — Generation flow 00:00 Intro 00:22 The four inputs (PDF, prefix, direction, protocol hint) 00:50 Spec build from PDF (clocks, params, coverage model) 01:50 Spec confirmation table 02:15 IVC generation — 22-file canonical UVM inventory 03:15 Verilator lint passes, first simulation FAILS 03:50 Snapshot, revise, single item-level constraint 04:50 Final report — PASS, 26 files, fully reproducible PART 2 — The generated code, file by file 05:46 File tree 05:56 Config object (PASSIVE default, checker ON, stress modes) 06:21 Interface + SVA bind (three clocking blocks) 06:41 Sequence item — the §3.1.2 TSTRB/TKEEP constraint 07:11 Initiator driver (reset-aware, timeout-bounded) 07:36 Coverage (spec-driven bins, protocol crosses) 07:43 Close ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━ WHAT YOU'RE LOOKING AT ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━ ▸ Protocol: AMBA 4 AXI4-Stream (ARM IHI0051A v1.0) ▸ Methodology: UVM (Accellera 1800.2-2017) ▸ Output: 22 SystemVerilog files — types pkg, interface, SVA bind, sequence item, config, sequencer, initiator + responder drivers, monitor, coverage, checker, agents, top pkg, plus sequence library, environment, three test variants, filelists, Verilator harness ▸ Validation: Verilator lint (zero warnings), full simulation (PASS after self-heal) ▸ Spec citations: every protocol-specific code path quotes the IHI0051A section it implements The fail/self-heal beat at 03:15–04:50 is the most important part of the demo: the IVC's own protocol checker flags illegal byte categorizations from its random sequence (TKEEP=0, TSTRB=1 — reserved per §3.1.2). The architect snapshots the failing IVC, routes to a revise sub-agent, and adds a single item-level constraint — `c_tstrb_subset_of_tkeep` — placed on the sequence item so every future randomize() call inherits the fix. ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━ ABOUT VOSKENAI ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━ VoskenAI is an AI-driven hardware design automation platform that generates silicon-readiness-verified SystemVerilog RTL and UVM verification IP from natural-language requirements and protocol specifications. Built on an open EDA toolchain: Verilator, cocotb, Yosys, SymbiYosys. ▸ Website: https://vosken.ai ▸ Contact: [email protected] If you're a verification team evaluating LLM-assisted flows and want to see VoskenAI run on your protocol or your IP, get in touch. #UVM #SystemVerilog #AXI4Stream #HardwareVerification #SemiconductorDesign #EDA #VerificationIP #RTLDesign #Verilator #FunctionalVerification #ChipDesign #DVEngineer